1. Field of the Invention
The invention relates to the field of semiconductor processing and more particularly to a method for decreasing the spacing between interconnect structures in an interconnect level.
2. Description of the Relevant Art
Integrated circuits typically include numerous conductors extending across the topography of a semiconductor. Conductors generally extend partially parallel to each other across the semiconductor topography. The conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide ("oxide"). Conductors are thereby lithographically patterned across the semiconductor topography, wherein the topography comprises a substrate with a dielectric placed thereon. Conductors are made from an electrically conductive material, a suitable material including Al, Ti, Ta, W, Mo, polysilicon, or a combination thereof. The substrate includes any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions. Typically, the substrate is a silicon-based material which receives p-type or n-type ions. Generally speaking, interconnect lines (or conductors) are fashioned upon the topography and dielectrically spaced above an underlying conductor or substrate. Each conductor is dielectrically spaced from other conductors within the same level of conductors (i.e., substantially coplanar conductors) by a defined lateral distance. Each conductor is designed to carry a certain amount of current, based on the desired design and application.
FIG. 1 illustrates interconnects 12 arranged upon a semiconductor topography 10, according to conventional design. Semiconductor topography 10 may include, e.g., an interlevel dielectric arranged above a semiconductor substrate. Interconnects 12 have been formed by depositing a conductive material across semiconductor topography 10, and thereafter etching regions of the conductive material from above topography 10. A photoresist masking layer had been patterned across the conductive material using optical lithography to define those regions of the conductive material to be removed. The regions of the conductive material exposed by the masking layer had been attacked during the etch technique. The masking layer, being resistant to attack by etchants, had effectively protected the underlying conductive material from being etched away. Unfortunately, the minimum lateral width l.sub.1 of each interconnect 12 and the minimum lateral distance l.sub.2 between a pair of the interconnects 12 is limited by the minimum feature size of the masking layer. Several factors affect the minimum dimensions of the masking layer features. One of these factors is the resolution, i.e., the ability to distinguish closely spaced objects, of the optical lithography system used to pattern the masking layer. The number of conductors arranged within a unitary level of an integrated circuit is limited by the dimension of each conductor and the distance between adjacent conductors. Therefore, the packing density of the conductors is somewhat sacrificed by the use of optical lithography to define the size of and spacing between the conductors.
As the complexity of integrated circuits has increased, an ever increasing number of interconnects are required to achieve the selective coupling of the transistors necessary to implement the desired circuit. The increase in the number of required interconnects, coupled with the minimum spacing tolerable between adjacent interconnect, has typically necessitated the use of multiple interconnect levels as described previously. Each additional interconnect level added to a semiconductor process increases the complexity, cost, and time required to produce a single integrated circuit. Therefore, it would be desirable to implement a semiconductor process that enables a decrease in spacing or an increase in the density at which the interconnects within a unitary interconnect level are spaced across an underlying topography.